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INTELLON CONFIDENTIAL
10
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Functional Description
The interfaces that provide data, status, and control to and from the INT5130 include…
•
External host interface provided via the Media Independent Interface (MII) format (described by
IEEE802.3u, Clause 22) or a General Purpose Serial Interface (GPSI).
•
Management control provided via the Management Data Interface (MDI) or the Serial Peripheral Interface
(SPI).
•
Analog Front End interface.
•
LEDs indicating network status.
•
Optional E
2PROM interface providing a path to initialize the INT5130 with PowerPacket-specific
configuration information.
•
The JTAG port implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
MII/GPSII
Interface
Interface
DMA
PHY
DMA
RISC uProcessor
Core
Link
Sequencer
ROM
RAM
Arbiter
Buffer
RAM
FIFOs
PHY
Core
PowerPacket MAC
PowerPacket PHY
MII or
GPSI
Interface Block
Config
Regs
MDI
or SPI
AFE
Logic
JTAG
LEDS
ADIO(9:0)
TEST
AGC(7:0)
PHY
Seq
SPI
Master
E2PROM
Figure 1: INT5130 Block Diagram
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