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C161 bảng dữ liệu(PDF) 68 Page - Infineon Technologies AG |
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C161 bảng dữ liệu(HTML) 68 Page - Infineon Technologies AG |
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68 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-20 1999-08 • MULIP-Flag: The MULIP-flag will be set to ’1’ by hardware upon the entrance into an interrupt service routine, when a multiply or divide ALU operation was interrupted before completion. Depending on the state of the MULIP bit, the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service. The MULIP bit is overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt-instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again after that. Note: The MULIP flag is a part of the task environment! When the interrupting service routine does not return to the interrupted multiply/divide instruction (i.e. in case of a task scheduler that switches between independent tasks), the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered. CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows to globally enable (IEN=’1’) or disable (IEN=’0’) interrupts. The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon entry into an interrupt service routine, but it can also be modified via software to prevent other interrupts from being acknowledged. In case an interrupt level '15' has been assigned to the CPU, it has the highest possible priority, and thus the current CPU operation cannot be interrupted except by hardware traps or external non-maskable interrupts. For details please refer to chapter “Interrupt and Trap Functions”. After reset all interrupts are globally disabled, and the lowest priority (ILVL=0) is assigned to the initial CPU activity. |
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