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EDS1232CASE bảng dữ liệu(PDF) 13 Page - Elpida Memory

tên linh kiện EDS1232CASE
Giải thích chi tiết về linh kiện  128M bits SDRAM (4M words x 32 bits)
PDF  53 Pages
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nhà sản xuất  ELPIDA [Elpida Memory]
Trang chủ  http://www.elpida.com/en
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EDS1232CASE bảng dữ liệu(HTML) 13 Page - Elpida Memory

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EDS1232CASE
Data Sheet E0351E30 (Ver. 3.0)
13
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Col.
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
Add
A10
BA0, BA1
/WE
/CAS
/RAS
/CS
CKE
CLK
H
(Bank select)
CBR (auto) Refresh Command



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