PUSB2X4D

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 1 — 5 November 2013

5 of 11

NXP Semiconductors

PUSB2X4D

ESD protection for high-speed interfaces

The device uses an advanced clamping structure, which shows a negative dynamic

resistance. This snap-back behavior strongly reduces the clamping voltage to the system

behind the ESD protection during an ESD event. Do not connect unlimited DC current

sources to the data lines to avoid keeping the ESD protection device in snap-back state

after exceeding breakdown voltage (due to an ESD pulse for instance).

Fig 4.

Dynamic resistance with positive clamping;

typical values

Fig 5.

Dynamic resistance with negative clamping,

typical values

Fig 6.

Dynamic resistance with positive clamping,

typical values

Fig 7.

Dynamic resistance with negative clamping;

typical values

05

4

23

1

aaa-009808

2

4

6

(A)

0

-3

0

-1

-2

aaa-009809

-4

-2

0

(A)

-6

aaa-009810

012

8

4

6

9

3

12

15

I

(A)

0

-8

0

-2

-6

-4

aaa-009811

-9

-6

-12

-3

0

I

(A)

-15