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74AXP1T34GS bảng dữ liệu(PDF) 1 Page - Nexperia B.V. All rights reserved

tên linh kiện 74AXP1T34GS
Giải thích chi tiết về linh kiện  Dual supply translating buffer
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1.
General description
The 74AXP1T34 is a dual supply translating buffer. It features one input (A), an output (Y)
and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is
referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be
supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any
voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
supply range and is fully specified for partial power down applications using IOFF. The IOFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2.
Features and benefits
Wide supply voltage range:
VCCI: 0.7 V to 2.75 V
VCCO: 1.2 V to 5.5 V
Low input capacitance; CI = 0.6 pF (typical)
Low output capacitance; CO = 1.8 pF (typical)
Low dynamic power consumption; CPD = 0.4 pF at VCCI = 1.2 V (typical)
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
Low static power consumption; ICCI = 0.5 A (85 C maximum)
Low static power consumption; ICCO = 1.8 A (85 C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V; A input)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
JESD8-C (2.7 V to 3.6 V; Y output)
JESD12-6 (4.5 V to 5.5 V; Y output)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V
74AXP1T34
Dual supply translating buffer
Rev. 1 — 22 December 2015
Product data sheet


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