LPC47M112 datasheet(32/208 Pages) SMSC

32 / 208 page

Enhanced Super I/O Controller with LPC Interface

Datasheet

SMSC DS – LPC47M112

Page 32

Rev. 02/02/2005

DATASHEET

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data

rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7

shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track

number to start precompensation. this starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and

data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset

or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the

runtime register block. Separator circuits will be turned off. The controller will come out of manual low power.

Table 7 - Precompensation Delays

PRECOMP

PRECOMPENSATION DELAY (nsec)

432

<2Mbps

2Mbps

111

001

010

011

100

101

110

000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

20.8

41.7

62.5

83.3

104.2

125

Default

Default: See Table 10

Table 8 - Data Rates

DRIVE RATE

DATA RATE

DENSEL

DRATE(1)

DRT1

DRT0

SEL1

SEL0

MFM

1Meg

---

500

250

300

150

250

125

1Meg

---

500

250

500

250

125

1Meg

---

500

250

2Meg

---

250

125

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