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74AXP1G04GS bảng dữ liệu(PDF) 1 Page - Nexperia B.V. All rights reserved

tên linh kiện 74AXP1G04GS
Giải thích chi tiết về linh kiện  Low-power inverter
PDF  17 Pages
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74AXP1G04GS bảng dữ liệu(HTML) 1 Page - Nexperia B.V. All rights reserved

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1.
General description
The 74AXP1G04 is a single inverting buffer.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications
using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2.
Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; CI = 0.5 pF (typical)
Low output capacitance; CO = 1.0 pF (typical)
Low dynamic power consumption; CPD = 2.3 pF at VCC = 1.2 V (typical)
Low static power consumption; ICC = 0.6 A (85 C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 Cto+85 C
74AXP1G04
Low-power inverter
Rev. 1 — 25 August 2014
Product data sheet


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