PUSB3F97 datasheet(8/14 Pages) NEXPERIA

tên linh kiện	PUSB3F97

Giải thích chi tiết về linh kiện	ESD protection for ultra high-speed interfaces

PDF	14 Pages

Scroll/Zoom	100%

nhà sản xuất	NEXPERIA [Nexperia B.V. All rights reserved]

Trang chủ	https://www.nexperia.com/

Logo

8 / 14 page

PUSB3F97

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 —

10 May 2017

8 of 14

Nexperia

PUSB3F97

ESD protection for ultra high-speed interfaces

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

IEC 61000-4-5; tp =8/20 s; positive pulse

IEC 61000-4-5; tp =8/20 s; negative pulse

Fig 11. Dynamic resistance with positive clamping;

typical values

Fig 12. Dynamic resistance with negative clamping;

typical values

tp = 100 ns; Transmission Line Pulse (TLP)

Fig 13. Dynamic resistance with positive clamping;

typical values

Fig 14. Dynamic resistance with negative clamping;

typical values

PUSB3F97 bảng dữ liệu(PDF) 8 Page - Nexperia B.V. All rights reserved