L9929 datasheet(9/23 Pages) STMICROELECTRONICS

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L9929

3Truth Table

Table 7. Truth Table

tdt

Transfer Delay (8)

(referred to master)

150

tSCKH

Serial clock high time (9)

(referred to master)

tSCKL

Access time (10)

(referred to master)

8.35

µs

Clock inactive before

chipselect becomes valid (11)

200

Clock inactive after

chipselect becomes valid (12)

200

trs

Rise-, fall time

Load on SO 50pF

TIMING

Diagnostic Threshold

(Open Load Detection DMS > 3.1V, EN < 18V and/or DI > 2V)

VOUT1

VOUT2

Load is available

0.8

VOUT1

VOUT2

Load is missing

0.8

IOUT2

IOUT1

Diagnostic Current

DMS > 3.1V, EN < 0.8V

EN < 18V and/or DI > 2V

700

1000

1500

1350

2000

µA

Tracking Diagnostic Current

IOUT1 / IOUT2

1.4

1.5

1.6

Delay Time

* After disabling the device, the

load has to be demagnetized

during tD ,to avoid erroneous OL

detection

100

Pos.

IN1

IN2

OUT1

OUT2

SF 3)

SPI 4)

DIA_REG

1. Forward

See

Diagnostics

/ Encoding

of Failures

2. Reverse

HLH

3. Free-wheeling low

4. Free-wheeling high

HHHH

5. Disable

6. Enable

7. IN1 disconnected

8. IN2 disconnected

9. DI disconnected

10. EN disconnected

11. Current limit. active

12. Undervoltage active1.)

13. Overtemperature 2.)

14. Overcurrent 2.)

Table 5. Electrical Characteristcs (continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

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