A63P0636

PRELIMINARY

(July, 2005, Version 0.0)

10

AMIC Technology, Corp.

AC Characteristics (continued)

Symbo

l

Parameter

-2.6

-2.8

-3.2

-3.5

-3.8

-4.2

Unit

Note

Min

.

Max

Min.

Max

Min

.

Max

Min

.

Max

Min.

Max

Min

.

Max

Hold Times

Address

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Address Status

( ADSC , ADSP )

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Address Advance ( ADV )

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Write Signal

( BW1 , BW2 , BW3 ,

BW4 , BWE , GW )

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Data-in

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Chip Enable

( CE , CE2, CE2 )

0.3

-

0.4

-

0.5

-

0.5

-

0.5

-

0.5

-

ns

7, 9

Notes:

1.

All voltages refer to GND.

2.

Overshoot:

Power-up:

≤ +3.6 and VCC ≤ 3.1V

for t

≤ 200ms

3.

4.

Test conditions assume the output loading shown in Figure 1, unless otherwise specified.

5.

±150mV from steady state voltage.

6.

7.

A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold

times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the

required setup and hold times.

8.

OE has no effect when a Byte Write enable is sampled LOW.

9.

This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and

hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be

valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.

AC I/O curves are available upon request.

11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means

device is active (not in POWER-DOWN mode).

12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage

current of 10

µA.

13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to

emerge from SLEEP mode to ensure no data is lost.