PCI6421 datasheet(191/204 Pages) TI

191 / 204 page

9−13

9.21 Power Management Data Register

The power management bridge support extension register provides extended power-management features not

applicable to the Smart Card controller; thus, it is read-only and returns 0 when read.

Bit

Name

Power management data

Type

Default

Power management data

Offset:

4Bh

Type:

Read-only

Default:

00h

9.22 General Control Register

This register controls this function. Information of this register can be read from the socket configuration register in

the Smart Card socket control register set. See Table 9−13 for a complete description of the register contents.

Bit

Name

General control

Type

Default

General control

Offset:

4Ch

Type:

Read/Write (EEPROM, GRST only)

Default:

0000h

Table 9−13. General Control Register

BIT

FIELD NAME

TYPE

DESCRIPTION

15−7

RSVD

Reserved. Bits 15−7 return 0s when read.

6−5 ‡

INT_SEL

Interrupt select. These bits are program the INTPIN register and set which interrupt output is used.

This field is ignored if one of the USE_INTx terminals is asserted.

00 = INTA (pin = 1)

01 = INTB (pin = 2)

10 = INTC (pin = 3)

11 = INTD (pin = 4)

4 ‡

D3_COLD

Disable function. Setting this bit to 1 hides this function. PCI configuration register of this function

must be accessible at any time. Clock (PCI and 48 MHz) to the rest of the function blocks must be

gated to reduce power consumption.

3−0

RSVD

Reserved. Bits 3−0 return 0s when read.

‡ One or more bits in this register are cleared only by the assertion of GRST.

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