PCI6421 datasheet(156/204 Pages) TI

156 / 204 page

7−12

7.18 Power Management Control and Status Register

The power management control and status register implements the control and status of the flash media controller.

This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See

Table 7−13 for a complete description of the register contents.

Bit

Name

Power management control and status

Type

RCU

Default

Power management control and status

Offset:

48h

Type:

Read/Clear, Read/Write, Read-only

Default:

0000h

Table 7−13. Power Management Control and Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15 ‡

PME_STAT

RCU

PME status. This bit defaults to 0.

14−13

DATA_SCALE

This field returns 0s, because the data register is not implemented.

12−9

DATA_SELECT

This field returns 0s, because the data register is not implemented.

8 ‡

PME_EN

PME enable. Enables PME signaling. assertion is disabled.

7−2

RSVD

Reserved. Bits 7−2 return 0s when read.

1−0 ‡

PWR_STATE

Power state. This 2-bit field determines the current power state and sets the flash media controller to

a new power state. This field is encoded as follows:

00 = Current power state is D0.

01 = Current power state is D1.

10 = Current power state is D2.

11 = Current power state is D3hot.

‡ One or more bits in this register are cleared only by the assertion of GRST.

7.19 Power Management Bridge Support Extension Register

The power management bridge support extension register provides extended power-management features not

applicable to the flash media controller; thus, it is read-only and returns 0 when read.

Bit

Name

Power management bridge support extension

Type

Default

Power management bridge support extension

Offset:

4Ah

Type:

Read-only

Default:

00h

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