EM78P259NP datasheet(21/88 Pages) EMC

21 / 88 page

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Product Specification (V1.0) 06.16.2005

• 15

(This specification is subject to change without further notice)

Bit 2 (CMPWE): Comparator wake-up enable bit

0 = Disable Comparator wake-up

1 = Enable Comparator wake-up

When Comparator enters sleep mode, this bit must be set to “Enable.“

Bit 1 (ICWE):

Port 5 input change to wake-up status enable bit

0 = Disable Port 5 input change to wake-up status

1 = Enable Port 5 input change to wake-up status

When Port 5 change enters sleep mode, this bit must be set to

“Enable.“

Bit 0:

Not implemented, read as ‘0’

6.1.15

RF (Interrupt Status 2 Register)

LPWTIF

HPWTIF

TCCCIF

TCCBIF

TCCAIF

EXIF

ICIF

TCIF

NOTE

■ “1” means interrupt request; “0” means no interrupt occurs.

■ RF can be cleared by instruction but cannot be set.

■ IOCF0 is the relative interrupt mask register.

■ Reading RF will result to "logic AND" of RF and IOCF0.

Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM

function. Reset by software.

Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM

function. Reset by software.

Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by

software.

Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by

software.

Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by

software.

Bit 2 (EXIF):

External interrupt flag. Set by falling edge on /INT pin. Reset by

software.

Bit 1 (ICIF):

Port 5 input status change interrupt flag. Set when Port 5 input

changes. Reset by software.

Bit 0 (TCIF):

TCC overflow interrupt flag. Set when TCC overflows. Reset by

software.

6.1.16

R10 ~ R3F

All of these are 8-bit general-purpose registers.

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