CS8421

16

DS641PP1

6.4

Bypass Mode

When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly

to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing

non-audio data through without a sample rate conversion. ILRCK and OLRCK should be the same sample

rate and synchronous in this mode.

6.5

Muting

The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the

output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is

unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes

invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or

SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft mut-

ed). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock.

Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being

set low, or illegal ratios between OLRCK and the XTI master clock. After all invalid states have been

cleared, the SRC will soft unmute SDOUT.

6.6

Group Delay and Phase Matching Between Multiple CS8421 Parts

The equation for the group delay through the sample rate converter is shown in “Digital Filter Character-

istics” on page 6. This phase delay is equal across multiple parts. Therefore, when multiple parts operate

at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.