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DSC1103 bảng dữ liệu(PDF) 2 Page - Microchip Technology

tên linh kiện DSC1103
Giải thích chi tiết về linh kiện  Low-Jitter Precision LVDS Oscillator
PDF  26 Pages
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DSC1103 bảng dữ liệu(HTML) 2 Page - Microchip Technology

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DSC1103/23
DS20005745B-page 2
 2017-2018 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
Input Voltage .......................................................................................................................................–0.3V to VDD+0.3V
ESD Protection (HBM) ...............................................................................................................................................4 kV
ESD Protection (MM) ................................................................................................................................................400V
ESD Protection (CDM) ............................................................................................................................................1.5 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Specifications: VDD = 3.3V; TA = +25°C unless otherwise specified.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Voltage (Note 1)VDD
2.25
—
3.63
V
—
Supply Current
IDD
—
—
0.095
mA
DSC1103, EN pin low; all
outputs disabled.
—20
22
DSC1123, EN pin low; all
outputs disabled.
Frequency Stability
∆f
——
±10
ppm
Includes frequency
variations due to initial
tolerance, temp., and power
supply voltage.
——
±20
——
±25
——
±50
Aging - First Year
∆fY1
—
—
±5
ppm
One year at +25°C
Aging - After First Year
∆fY2+
—
—
<±1
ppm/yr
Year two and beyond at
+25°C
Start-up Time (Note 2)tSU
—
—
5
ms
T = +25°C
Input Logic Levels
VIH
0.75 x VDD
——
V
Input logic high
VIL
—
—
0.25 x VDD
Input logic low
Output Disable Time (Note 3)tDA
——
5
ns
—
Output Enable Time
tEN
—
—
5
ms
DSC1103
—
—
20
ns
DSC1123
Enable Pull-Up Resistor
(Note 4)
RPU
—40
—
kΩ
Pull-up resistor exist.
LVDS Outputs
Supply Current
IDD
—
29
32
mA
Output enabled, RL = 100Ω
Output Offset Voltage
VOS
1.125
—
1.4
V
R = 100Ω Differential
Delta Offset Voltage
∆VOS
——
50
mV
—
Peak-to-Peak Output Swing
VPP
—
350
—
mV
Single-Ended
Note 1: VDD pin should be filtered with a 0.1 µF capacitor.
2: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
3: See the Output Waveform section and the Test Circuit for more information.
4: Output is enabled if pad is floated or not connected.



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