2

4318C–ULC–08/05

ATU18

The ATU18 series provide several options for output buffers, including a variety of drive levels

up to 24mA. Schmitt trigger inputs are also available. A number of techniques are used to

improve noise immunity and to reduce EMC emissions, including several independent power

supply buses and internal decoupling for isolation.

The ATU18 series are designed to allow conversion of high performance 1.8V devices. Support

of mixed supply conversions is also possible, allowing optimal trade–offs between speed and

power consumption.

Array

Organization

Architecture

The ATMEL 0.18um matrices allow conversions of designs being developed on Altera/Apex-

contains configurable memory DPRAM blocks, PLLs (from 2 to 4) and Power-on-Reset. It can

also integrate a 1.8V regulator from 3.3V supply if no available 1.8V on the board. The associ-

ated Physical synthesis/optimization flow contributes to achieve high speed designs, even

improving drastically the application frequency and power consumption.

Table 1. Matrices

Part Number

Max Pads

Gates

DPRAM bits

PLL

ATU18_680

680

1000K

847K

4

ATU18_600

600

720K

700K

4

ATU18_484

484

486K

460K

2

ATU18_432

432

330K

350K

2

ATU18_352

352

276K

221K

2

ATU18_304

304

171K

183K

2

ATU18_256

256

111K

147K

2

ATU18_160

160

45K

55K

1