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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DM368ZCEZ bảng dữ liệu(PDF) 68 Page - Texas Instruments |
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DM368ZCEZ bảng dữ liệu(HTML) 68 Page - Texas Instruments |
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68 / 208 page  TMS320DM368 SPRS668C – APRIL 2010 – REVISED JUNE 2011 www.ti.com Table 3-14. AECFG (Async EMIF Configuration) Coding at Boot Time 000 001 010 100 101 110 GPIO[65] EM_A[14] EM_BA[0] GPIO[65] EM_A[14] EM_BA[0] GPIO[66] EM_BA[1] EM_BA[1] GPIO[66] EM_BA[1] EM_BA[1] GPIO[67] EM_A[0] EM_A[0] GPIO[67] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[68] EM_A[3] EM_A[3] GPIO[68] EM_A[3] EM_A[3] GPIO[69] EM_A[4] EM_A[4] GPIO[69] EM_A[4] EM_A[4] GPIO[70] EM_A[5] EM_A[5] GPIO[70] EM_A[5] EM_A[5] GPIO[71] EM_A[6] EM_A[6] GPIO[71] EM_A[6] EM_A[6] GPIO[72] EM_A[7] EM_A[7] GPIO[72] EM_A[7] EM_A[7] GPIO[73] EM_A[8] EM_A[8] GPIO[73] EM_A[8] EM_A[8] GPIO[74] EM_A[9] EM_A[9] GPIO[74] EM_A[9] EM_A[9] GPIO[75] EM_A[10] EM_A[10] GPIO[75] EM_A[10] EM_A[10] GPIO[76] EM_A[11] EM_A[11] GPIO[76] EM_A[11] EM_A[11] GPIO[77] EM_A[12] EM_A[12] GPIO[77] EM_A[12] EM_A[12] GPIO[78] EM_A[13] EM_A[13] GPIO[78] EM_A[13] EM_A[13] GPIO[57] GPIO[46] GPIO[46] EM_D[8] EM_D[8] EM_D[8] GPIO[58] GPIO[47] GPIO[47] EM_D[9] EM_D[9] EM_D[9] GPIO[59] GPIO[48] GPIO[48] EM_D[10] EM_D[10] EM_D[10] GPIO[60] GPIO[49] GPIO[49] EM_D[11] EM_D[11] EM_D[11] GPIO[61] GPIO[50] GPIO[50] EM_D[12] EM_D[12] EM_D[12] GPIO[62] GPIO[51] GPIO[51] EM_D[13] EM_D[13] EM_D[13] GPIO[63] GPIO[52] GPIO[52] EM_D[14] EM_D[14] EM_D[14] GPIO[64] GPIO[53] GPIO[53] EM_D[15] EM_D[15] EM_D[15] 3.7.5.2 AEMIF Timing Configuration When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is 88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz clock at MXI/MXO, the AEMIF is configured to run at (12 MHz/ 88) which equals approximately 136.36 kHz. 3.7.6 Oscillator Frequency Configuration The oscillator input pins, MXI1, MXO, are designed to operate in two frequency ranges depending on the GIO81(OSCCFG) pin sampled at reset, which should be set according to the required input frequency of operation. See Table 3-15 for details. Table 3-15. Operation Frequency MODE GIO81 (OSCCFG) OSCILLATION 1 0 15 - 35MHz 2 1 30 - 40MHz The frequency selection pin cannot be changed dynamically while the oscillator is running. They should only be set once before oscillator startup. The GIO81(OSCCFG) state is latched during reset, and it specifies the oscillation frequency mode as shown in Table 3-15. 68 Device Configurations Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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