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DSC12X2 bảng dữ liệu(PDF) 3 Page - Microchip Technology |
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DSC12X2 bảng dữ liệu(HTML) 3 Page - Microchip Technology |
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3 / 32 page ![]() 2019 Microchip Technology Inc. DS20006011A-page 3 DSC12X2/3/4 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Supply Voltage .......................................................................................................................................... –0.3V to +4.0V Input Voltage .....................................................................................................................................–0.3V to VDD + 0.3V ESD Protection (HBM) ............................................................................................................................................... 4 kV ESD Protection (MM) ................................................................................................................................................400V ESD Protection (CDM) ............................................................................................................................................ 1.5 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Characteristics: VDD = 2.5V ±10% or 3.3V±10%; TA = –40°C to +105°C, unless noted. Parameter Symbol Min. Typ. Max. Units Conditions Supply Voltage VDD 2.25 — 3.63 V Note 1 Supply Current IDD —50— mA LVPECL, fOUT = 100 MHz —32— LVDS, fOUT = 100 MHz — 40 — HCSL, fOUT = 100 MHz —23 — Output disabled (tri-state), fOUT = 100 MHz Standby Current ISTDBY_ —2.5 5 µA Input pin = STDBY = Asserted (VDD = 3.3V) Frequency Stability ∆f —— ±20 ppm Includes frequency variations due to initial tolerance, temp., and power supply voltage —— ±25 —— ±50 Startup Time tSU —5.5 6 ms From 90% VDD to valid clock output, T = +25°C, Note 2 Input Logic Levels VIH 0.75 x VDD —— V Input logic high VIL —— 0.25 x VDD Input logic low Output Disable Time tDA — — 25 ns Note 3 Output Enable Time tEN —— 6 ms STDBY —— 350 ns OE Enable Pull-Up Resistor — — 1.5 — MΩ Pull-up resistor on pin 1, Note 4 LVPECL (DSC12x2) Frequency f0 2.5 — 450 MHz — Output Logic Levels VOH VDD – 1.145 —— VRL = 50Ω VOL —— VDD – 1.695 Peak-to-Peak Output Swing VPP — 800 — mV Single-Ended Output Transition Time tR —200 250 ps 20% to 80%, RL = 50Ω tF —250 300 Output Duty Cycle SYM 48 — 52 % Differential Period Jitter RMS JPER —2.0 — ps f0 = 156.25 MHz, 10k cycles |
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