VSC8504-02 datasheet(107/131 Pages) MICROSEMI

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Electrical Specifications

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

5.2.3

SerDes Outputs

The values listed in the following table are valid for all configurations, unless otherwise noted.

Recovered clock cycle

time

tRCYC

32.0

Recovered clock cycle

time

tRCYC

40.0

Frequency stability

ƒSTABILITY

ppm

Duty cycle, master

mode

Clock rise time and

fall time

tR, tF

600

20% to 80%

Peak-to-peak jitter,

copper media

interface (1000BASE-

T slave mode)

JPPCLK_Cu

400

10K samples

Peak-to-peak jitter,

fiber media interface,

100BASE-FX

JPPCLK_FiFX

1.2

10K samples

Peak-to-peak jitter,

fiber media interface,

1000BASE-X

JPPCLK_FiX

250

10K samples

Table 109 •

SerDes Outputs AC Specifications

Parameter

Symbol

Minimum

Maximum

Unit

Condition

VOD ringing compared to

VS, SGMII mode

VRING

±10

RL = 100

Ω ±1%

VOD rise time and fall time,

SGMII mode

tR, tF

100

200

20% to 80% of VS

RL = 100

Ω ±1%

Differential peak-to-peak

output voltage

VOD

Tx disabled

Differential output return

loss, 50 MHz to 625 MHz

RLO_DIFF

≥10

RL = 100

Ω ±1%

Differential output return

loss, 625 MHz to

1250 MHz

RLO_DIFF

10–10 × log

(ƒ/625 MHz)

RL = 100

Ω ±1%

Common-mode return

loss, 50 MHz to 625 MHz

RLOCM

6dB

Interpair skew, SGMII

mode

tSKEW

Table 108 •

Recovered Clock AC Characteristics (continued)

Parameter

Symbol

Minimum

Typical Maximum

Unit Condition

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