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STUSB4500 bảng dữ liệu(PDF) 15 Page - STMicroelectronics |
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STUSB4500 bảng dữ liệu(HTML) 15 Page - STMicroelectronics |
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15 / 41 page ![]() 3.6 High voltage protections The STUSB4500 can be safely used in systems or connected to systems that handle high voltage on the VBUS power path. The device integrates an internal circuitry on the CC pins that tolerates high voltage and ensures protection up to 22 V in case of unexpected short-circuits with the VBUS or in case of a connection to a device supplying high voltage on the VBUS. 3.7 Hardware fault management The STUSB4500 handles during system operation some pre-identified hardware fault conditions. When such conditions happen, the circuit goes into a transient error recovery state named ErrorRecovery in the Type-C FSM as defined in the USB Type-C standard specifications. The error recovery state is equivalent to force a detach event. When entering in this state, the device de-asserts the VBUS power path by disabling the VBUS_EN_SNK, POWER_OK2 and POWER_OK3 pins, and it removes the terminations from the CC pins during several tens of milliseconds. Then, it transitions to the unattached state. The STUSB4500 goes into error recovery state when at least one condition listed below is met: • If an overtemperature is detected (junction temperature above maximum TJ) • If an overvoltage is detected on the CC pins (voltage on CC pins above VOVP) • If after a hard reset the power delivery communication with the source is broken The detection of a hardware fault is advertised through the GPIO pin when configured in ERROR_RECOVERY mode. See Section 7 Electrical characteristics for threshold values. 3.8 Debug accessory mode detection The STUSB4500 detects a connection to a debug and test system (DTS) as defined in the USB Type-C standard specification. The debug accessory detection is advertised through the GPIO pin when configured in DEBUG mode. A debug accessory device is detected when both the CC1 and CC2 pins are pulled up by an Rp resistor from the connected device. The voltage levels on the CC1 and CC2 pins give the orientation and current capability as described in the table below. The GPIO pin configured in DEBUG mode is asserted to advertise the DTS detection and the A_B_SIDE pin indicates the orientation of the connection. Table 11. Orientation and current capability detection in sink power role # CC1 pin (CC2 pin) CC2 pin (CC1 pin) Charging current configuration A_B_SIDE pin CC1/CC2 (CC2/CC1) 1 Rp 3 A Rp 1.5 A Default Hi-Z (0) 2 Rp 1.5 A Rp default 1.5 A Hi-Z (0) 3 Rp 3 A Rp default 3.0 A Hi-Z (0) 4 Rp def/1.5 A/3 A Rp def/1.5 A/3 A Default Hi-Z (Hi-Z) STUSB4500 High voltage protections DS12499 - Rev 2 page 15/41 |
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