STM32L4A6RG datasheet(59/282 Pages) STMICROELECTRONICS

59 / 282 page

DS11584 Rev 8

59/282

STM32L4A6xG

Functional overview

The synchronization for this oscillator can also be taken from the USB data stream itself

(SOF signalization) which allows crystal less operation.

The major features are:

•

Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

•

12 host channels with periodic OUT support

•

HNP/SNP/IP inside (no need for any external resistor)

•

USB 2.0 LPM (Link Power Management) support

•

Battery Charging Specification Revision 1.2 support

•

Internal FS OTG PHY support

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected.

3.40

Clock recovery system (CRS)

The STM32L4A6xG devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from USB SOF signalization, from LSE oscillator, from an

external signal on CRS_SYNC pin or generated by user software. For faster lock-in during

startup it is also possible to combine automatic trimming with manual trimming action.

3.41

Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes two memory controllers:

•

The NOR/PSRAM memory controller

•

The NAND/memory controller

This memory controller is also named Flexible memory controller (FMC).

The main features of the FMC controller are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

–

NOR Flash memory/OneNAND Flash memory

–

PSRAM (4 memory banks)

–

NAND Flash memory with ECC hardware to check up to 8 Kbyte of data

•

8-,16- bit data bus width

•

Independent Chip Select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

•

The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

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