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PTMP6131DYAT bảng dữ liệu(PDF) 21 Page - Texas Instruments

tên linh kiện PTMP6131DYAT
Giải thích chi tiết về linh kiện  TMP61 Small Silicon-Based Linear Thermistor for Temperature Sensing
PDF  36 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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PTMP6131DYAT bảng dữ liệu(HTML) 21 Page - Texas Instruments

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Temperature (qC)
-60
-40
-20
0
20
40
60
80
100 120 140 160
0
0
1
0.8
2
1.6
3
2.4
4
3.2
5
4
6
4.8
7
5.6
d011
VTemp (IBIAS= 200 PA)
VTemp (VBIAS = 2 V)
Error (qC) (IBIAS = 200 PA)
Error (qC) (VBIAS = 2 V)
Temperature (qC)
0
25
50
75
100
125
150
0
1
2
3
4
5
6
D014
21
TMP61
www.ti.com
SBOS921C – DECEMBER 2018 – REVISED SEPTEMBER 2019
Product Folder Links: TMP61
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Typical Application (continued)
Figure 20. Thermal Foldback Voltage Output Curve
9.2.1.3 Application Curve
The TMP61 accuracy varies depending on the selected biasing circuit. This variation can be seen in Figure 21.
VTEMP is shown with either VBIAS at 2 V in a resistor divider circuit (RBIAS = 10 kΩ ±1%), or IBIAS at 200 µA. Supply
sources used are assumed to be ideal. The best accuracy is achieved using a direct current bias method.
Figure 21. TMP61 Voltage Output and Temperature Error Based on the Bias Method
10 Power Supply Recommendations
The maximum recommended operating voltage of the TMP61 is 5.5 V (VSns), and the maximum current through
the device is 400 µA (ISns).
11 Layout
11.1 Layout Guidelines
The layout of the TMP61 is similar to that of a passive component. If the device is biased with a current source,
the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the circuit is
biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is connected
to ground and V+ is connected to the output, VTEMP. If the device is placed on the upper side of the divider, V+ is
connected to the voltage source and V– is connected to the output voltage, VTEMP. Figure 22 shows the device
layout.



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