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ST72311J2 bảng dữ liệu(PDF) 83 Page - STMicroelectronics

tên linh kiện ST72311J2
Giải thích chi tiết về linh kiện  8-BIT MCU WITH 8 TO 16K ROM/OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST72311J2 bảng dữ liệu(HTML) 83 Page - STMicroelectronics

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ST72311
PERIPHERAL CHARACTERISTICS (Cont’d)
Serial Peripheral Interface
Ref.
Characteristics
Configuration
Symbol
Value
Unit
Min.
Max.
SPI Frequency
Master
fSPI(m)
fCPU
Slave
fSPI(s)
dc
fCPU
1
Cycle Time
Master
tCYC(m)
4
500
CC
ns
Slave
tCYC(s)
2
250
CC
ns
2
Enable Lead Time
Master
tLEAD(m)
ns
Slave
tLEAD(s)
120
ns
3
Enable Lag time
Master
ns
Slave
120
ns
4
Clock (SCK)High Time
Master
tW(SCKH)
100
ns
Slave
tW(SCKH)
90
ns
5
Clock (SCK) Low Time
Master
tW(SCKL)
100
ns
Slave
tW(SCKL)
90
ns
6
Data Set-up Time
Master
tSU(m)
100
ns
Slave
tSU(s)
100
ns
7
Data Hold Time (Inputs)
Master
tH(m)
100
ns
Slave
tH(s)
100
ns
8
Access Time (Time to Data Active
from High Impedance State)
Slave
tA
0
120
ns
9
Disable Time (Hold Time to High
Impedance State)
Slave
tDIS
240
ns
10
Data Valid
Master (Before Capture
Edge)
tV(m)
0.25
tCYC(m)
Slave (After Enable Edge)
tV(s)
120
ns
11
Data Hold Time (Outputs)
Master (Before Capture
Edge)
tHO(m)
0.25
tCYC(m)
Slave (After Enable Edge)
tHO(s)
0ns
12
Rise Time (20% VDD to 70% VDD,
CL = 200pF)
SPI Outputs (SCK, MOSI,
MISO)
tRM
100
ns
SPI Inputs (SCK, MOSI, MI-
SO, SS)
tRS
2.0
µs
13
Fall Time (70% VDD to 20% VDD, CL
= 200pF)
SPI Outputs (SCK, MOSI,
MISO)
tFM
100
ns
SPI Inputs (SCK, MOSI, MI-
SO, SS)
tFS
2.0
µs
1
128
----------
1
4
---
1
2
---
83



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