S-8211CDN-M5T1U datasheet(17/43 Pages) ABLIC

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BATTERY PROTECTION IC FOR 1-CELL PACK

Rev.7.7_03

S-8211C Series



Test Circuits

Caution Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (VCO) and DO pin (VDO) are

judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to

VVM and the DO pin level with respect to VSS.

1. Overcharge detection voltage, overcharge release voltage

(Test condition 1, test circuit 1)

Overcharge detection voltage (VCU) is defined as the voltage between the VDD pin and VSS pin at which VCO goes

from "H" to "L" when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V. Overcharge

release voltage (VCL) is defined as the voltage between the VDD pin and VSS pin at which VCO goes from "L" to "H"

when the voltage V1 is then gradually decreased. Overcharge hysteresis voltage (VHC) is defined as the difference

between overcharge detection voltage (VCU) and overcharge release voltage (VCL).

2. Overdischarge detection voltage, overdischarge release voltage

(Test condition 2, test circuit 2)

Overdischarge detection voltage (VDL) is defined as the voltage between the VDD pin and VSS pin at which VDO goes

from "H" to "L" when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V, V2 = 0 V.

Overdischarge release voltage (VDU) is defined as the voltage between the VDD pin and VSS pin at which VDO goes

from "L" to "H" when the voltage V1 is then gradually increased. Overdischarge hysteresis voltage (VHD) is defined as

the difference between overdischarge release voltage (VDU) and overdischarge detection voltage (VDL).

3. Discharge overcurrent detection voltage

(Test condition 3, test circuit 2)

Discharge overcurrent detection voltage (VDIOV) is defined as the voltage between the VM pin and VSS pin whose

delay time for changing VDO from "H" to "L" lies between the minimum and the maximum value of discharge

overcurrent delay time when the voltage V2 is increased rapidly (within 10

s) from the starting condition of

V1 = 3.5 V, V2 = 0 V.

4. Load short-circuiting detection voltage

(Test condition 3, test circuit 2)

Load short-circuiting detection voltage (VSHORT) is defined as the voltage between the VM pin and VSS pin whose

delay time for changing VDO from "H" to "L" lies between the minimum and the maximum value of load short-circuiting

delay time when the voltage V2 is increased rapidly (within 10

s) from the starting condition of V1 = 3.5 V, V2 = 0 V.

5. Charge overcurrent detection voltage

(Test condition 4, test circuit 2)

Charge overcurrent detection voltage (VCIOV) is defined as the voltage between the VM pin and VSS pin whose delay

time for changing VCO from "H" to "L" lies between the minimum and the maximum value of charge overcurrent delay

time when the voltage V2 is decreased rapidly (within 10

s) from the starting condition of V1 = 3.5 V, V2 = 0 V.

6. Current consumption during operation

(Test condition 5, test circuit 2)

The current consumption during operation (IOPE) is the current that flows through the VDD pin (IDD) under the set

conditions of V1 = 3.5 V and V2 = 0 V (normal status).

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