STR720 datasheet(382/401 Pages) STMICROELECTRONICS

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STR720 - ELECTRICAL CHARACTERISTICS

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28.7.3

PLL Characteristics

STR720 implements a PLL which combines different levels of frequency dividers with a

Voltage Controlled Oscillator (VCO) working as frequency multiplier. On chip PLL is used to

generate system clock from an external reference clock signal. Its characteristics in term of

generated clock accuracy depends heavily on the input signal and power supply quality.

In the following table, jitter is intended as the difference of the TMAX and TMIN, where TMAX is

maximum time period of the PLL output clock and TMIN is the minimum time period of the PLL

output clock. The value is expressed as ratio with respect to the average/nominal time period

of PLL output clock.

Jitter at the PLL output can be due to the many different reasons, the major contributors being

noise on input reference clock and noise on PLL supply (internally or externally generated).

PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the

frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency

jitter (frequency > PLL bandwidth) is attenuated @20dB/decade. This is the reason why,

depending on input clock noise spectral characteristics, jitter performance can be better when

PLL output is used as system clock than when PLL is bypassed.

Digital supply noise adds deterministic components to the PLL output jitter, independent on

multiplication factor. Its effects is strongly reduced thanks to particular care used in the

physical implementation and integration of the PLL module inside the device. Particular care

is thus recommended in board design for what concerns VDDPLL and clock routing.

Figure 75. Typical Application with External Clock Source

fCK

VILP

VIHP

tr(P)

tf(P)

tw(HP)

tw(LP)

90%

10%

VREF

CLK

STR720

VREF

EXTERNAL CLOCK

SOURCE

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