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STR720 bảng dữ liệu(PDF) 381 Page - STMicroelectronics

tên linh kiện STR720
Giải thích chi tiết về linh kiện  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
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STR720 bảng dữ liệu(HTML) 381 Page - STMicroelectronics

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STR720 - ELECTRICAL CHARACTERISTICS
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28.7.2
CLK pad characteristics (External Clock Source)
These pads are used to provide clock signal to STR720 system from an external clock source.
Since their electrical characteristics are different from normal I/O pads they are hereafter
reported in a specific table.
1.
VDD(all) = 1.80 V ± 10%, VDD3(all) = 3.30 V ± 10%, TA = -40 / +85 °C unless otherwise specified.
2.
Data based on design guidelines and validation, not tested in production.
Table 94. DC CLK pad characteristics
Symbol
Parameter
Test Conditions(1)
Value
Unit
Min
Typ
Max
VDD3P
Supply Voltage for CLK input
buffer.
3.14
3.30
3.47
V
VREF
Reference Voltage for CLK
input signal (2)
VREF =(VDD3P -1)*0.9
±
± 60 mV
1.87
2.1
2.28
V
VREF_R
Recommended reference Volt-
age for CLK input signal
1.6
-
2.0
V
VIHP
(CLK)
Main CLK Clock (CLK) Input
high level (2)
See Figure 75
VREF + 0.2
-
-
V
VILP
(CLK)
Main CLK Clock (CLK) Input
low level (2)
See Figure 75
--
VREF - 0.2
V
Table 95. AC CLK pad characteristics
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
tw(HP)
tw(LP)
Main CLK Clock (CLK) high or
low time (2)
See Figure 75
14.29
-
-
ns
tr(P)
tf(P)
Main CLK Clock (CLK) rise or
fall time (2)
See Figure 75
--
7
ns
IL
CLK Input leakage current
VSS ≤ VIN ≤ VDD3P
--
±1
µA
IDD3P_R
VDD3P RUN/IDLE mode cur-
rent
-2.75-
mA
IDD3P_S
VDD3P SLOW/STOP mode
current
-
-
10
nA



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