STR720 datasheet(209/401 Pages) STMICROELECTRONICS

209 / 401 page

STR720 - CONTROLLER AREA NETWORK (CAN)

209/401

18.5 Register Description

The CAN Peripheral allocates an address space of 256 bytes. The registers are organized as

16-bit registers.

The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM.

They buffer the data to be transferred to and from the RAM, avoiding conflicts between CPU

accesses and message reception/transmission.

In this section, the following abbreviations are used:

The CAN registers are listed in Table 48.

read/write (rw)

The software can read and write to these bits.

read-only (r)

The software can only read these bits.

write-only (w)

The software should only write to these bits.

Table 48. CAN Registers

Address Offset

Reset Value

CAN Control Register (CAN_CR)

00h

0001h

Status Register (CAN_SR)

04h

0000h

Error Counter (CAN_ERR)

08h

0000h

Bit Timing Register (CAN_BTR)

0Ch

2301h

Test Register (CAN_TESTR)

14h

0000 0000 R000

0000 b

BRP Extension Register (CAN_BRPR)

18h

0000h

IFn Command Request Registers (CAN_IFn_CRR)

20h (CAN_IF1_CRR),

80h (CAN_IF2_CRR)

IFn Command Mask Registers (CAN_IFn_CMR)

24h (CAN_IF1_CMR),

84h (CAN_IF2_CMR)

0000h

IFn Mask 1 Register (CAN_IFn_M1R)

28h (CAN_IF1_M1R),

88h (CAN_IF2_M1R)

FFFFh

IFn Mask 2 Register (CAN_IFn_M2R)

2Ch (CAN_IF1_M2R),

8Ch (CAN_IF2_M2R)

FFFFh

IFn Message Arbitration 1 Register (CAN_IFn_A1R)

30h (CAN_IF1_A1R), 90h

(CAN_IF2_A1R)

0000h

IFn Message Arbitration 2 Register (CAN_IFn_A2R)

34h (CAN_IF1_A2R), 94h

(CAN_IF2_A2R)

0000h

IFn Message Control Registers (CAN_IFn_MCR)

38h (CAN_IF1_MCR),

98h (CAN_IF2_MCR)

0000h

IFn Data A/B Registers (CAN_IFn_DAnR and CAN_IFn_DBnR)

Interrupt Identifier Register (CAN_IDR)

10h

0000h

Transmission Request Registers 1 & 2 (CAN_TxRnR)

100h (CAN_TxR1R),

104h (CAN_TxR2R)

0000 0000h

New Data Registers 1 & 2 (CAN_NDnR)

120h (CAN_ND1R), 124h

(CAN_ND2R)

0000 0000h

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