STR720 datasheet(197/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

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of FIFO locations enabled by TFE[3:0]. The flag is set immediately after the data write is

complete.

Bit 7 = TUFL: Transmit Underflow.

This status bit gets set only when BSPI is configured in master mode, when the TFE bit is set

and, by the time the Transmit Data Register contents are to be transferred to the shift register

for the next transmission, the processor has not yet put the data for transmission into the

Transmit Data Register.

TUFL is set on the first edge of the clock when CPHA = 1 and when CPHA = 0 on the

assertion of SS. If TIE[1:0] bits are set to “10” then, when TUFL gets set, an interrupt will be

asserted to the processor.

Note

From an application point of view, it is important to be aware that the first word

available after an underflow event has occurred should be ignored, as this data was

loaded into the shift register before the underflow condition was flagged.

Bit 6 = TFE: Transmit FIFO Empty.

This bit gets set whenever the Transmit FIFO has transferred its last data word to the transmit

buffer. If interrupts are enabled then an interrupt will be asserted whenever the last word has

been transferred to the transmit buffer.

Bit 5 = ROFL: Receiver Overflow.

This bit gets set if the Receive FIFO is full and has not been read by the processor by the time

another received word arrives. If the REIE bit is set then, when this bit gets set an interrupt will

be asserted to the processor. This bit is cleared when a read takes place of the CSR register

and the FIFO.

Bit 4 = RFF: Receive FIFO Full.

This status bit indicates that the number of FIFO locations, as defined by the RFE[3:0] bits,

are all full, i.e. if the FIFO is 4 deep then all data has been received to all four locations.

If the RIE[1:0] bits are configured as ‘11’ then, when this status bit gets set, an interrupt will be

asserted to the processor. This bit is cleared when at least one data word has been read.

Bit 3 = RFNE: Receive FIFO Not Empty.

This status bit indicates that there is data in the Receive FIFO. It is set whenever there is at

least one block of data in the FIFO i.e. for 8-bit mode 8 bits and for 16-bit mode 16 bits. If the

RIE[1:0] bits are configured to ‘01’ then whenever this bit gets set an interrupt will be asserted

to the processor. This bit is cleared when all valid data has been read out of the FIFO.

Bit 2 = BERR: Bus Error.

This status bit indicates that a Bus Error condition has occurred, i.e. that more than one

device has acted as a Master simultaneously on the BSPI bus. A Bus Error condition is

defined as a condition where the Slave Select line goes active low when the module is

configured as a Master, provided that MASK_SS bit in BSPCSR3 register is not set. This

indicates contention in that more than one node on the BSPI bus is attempting to function as

a Master. This bit is cleared when the Slave Select line is deasserted, MASK_SS bit is set or

Slave mode is selected.

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