STR720 datasheet(162/401 Pages) STMICROELECTRONICS

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STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG)

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the Peripheral Address Error Register. This should allow the user to retrieve the event which

generated the error.

15.3.1

Peripherals clock gating

The AHB/APB bridge enables to configure the peripherals’ clocks to be switched-on/off. The

32-bits Peripheral Clock Gating registers (PCGn) enables to switch-off/on any of the 13

peripherals directly. This enables to centralize the management of all the clock on this APB

bus.

When a peripheral’s clock is switched-off, any access to this peripheral will return an error on

the AHB bus. The Bus Status Register will contain the error status, the Peripheral Address

Error Register will provide the address who generated the error.

In order to help debugging real-time application, register EMU_PCGn has been introduced.

The status of this register is used to force the gating of the corresponding clock line when the

system enter into debug mode, based upon the following definition:

0 -> Peripheral clock switched off in debug mode.

1 -> Peripheral clock status depends on PCGn bit also in debug mode.

15.3.2

Peripherals reset control

The AHB/APB bridge has a unique reset pin that enables resetting the AHB/APB bridge as

well as all peripherals. As the reset removal is aligned with AHB clock, the AHB/APB bridge

provides a re-synchronization mechanism to generate the peripherals reset. The reset is

asserted asynchronously and then released synchronously with the APB clock.

Moreover, the AHB/APB bridge enables to configure the peripherals’ reset in order to reset

independently any of the peripherals. The 32-bits Peripheral Reset Control registers (PRCn)

enables to reset any of the 13 peripherals directly. This allows to centralize the management

of all the reset on this APB bus.

When a peripheral is under reset, any access to this peripheral will return an error on the AHB

bus. The Bus Status Register will contain the error status, the Peripheral Address Error

15.4 Register description

The AHB/APB bridge provides a set of registers to configure peripherals clock gating, access

control and monitor the AHB/APB bridge status. These registers are mapped as peripheral #0

in the AHB/APB bridge mapping.

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