STR720 datasheet(158/401 Pages) STMICROELECTRONICS

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STR720 - REAL TIME CLOCK (RTC)

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14.4.1

RTC registers are mapped as 16 bit addressable registers as described in the table below:

Refer to Table 21 on page 50 for the base address.

14.5 Programming considerations

RTC configuration procedure can be described by the following steps:

1. Reading RTOFF until its value is ‘1.

2. Writing CNF control bit at ‘1’.

3. Writing one or more RTC registers.

4. Writing CNF control bit at ‘0’, along with any other required RTCCR change.

5. Read back updated register for confirmation.

The writing operation actually takes effect only when CNF bit is written back to ‘0’ and it needs

at least 2 cycles of CLK_AF to be terminated. During those 2 CLK_AF cycles, all RTC

registers are updated simultaneously, so the sequence used to write them during the

configuration phase is not relevant. There are no particular constraints about the total length

of configuration procedure, as the actual update of the registers happens only when CNF bit is

reset to ‘0’.

Note

The configuration procedure described above should be executed by a routine

located in internal RAM so to avoid any possible interaction between RTC register

update and the board noise induced by external memory access, especially when

the code is executed from external SDRAM memory. RTC register update sequence

is quite sensitive to noise induced on the clock oscillator, and unexpected reset of

RTOFF bit could occur if such interaction happens. In this case resetting RTC block

by using RTCRST pin will restore normal RTC operations.

It is important to consider that once CNF bit is reset to ‘0’ and the actual update begins, none

of the RTC registers can be modified, RTCCR included, until the update terminates (RTOFF

becomes ‘1’ again). Since this period of time is quite long in terms of CPU clock periods (it is

Table 40. RTC Register Map

Addr.

Offset

765432

RTCCR

Reserved

GEN

PEREN

AEN

Res..

Reserved

RT OFF

CNF

GIR

PERIR

AIR

Res..

RTCCNT_L

CNT_L

RTCCNT_M

CNT_M

RTCCNT_H

CNTH

RTCA_L

ALARM_L

RTCA_M

ALARM_M

RTCA_H

ALARM_H

RTCP_L

PERIOD_L

RTCP_H

Reserved

PERIOD_H

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