IDTCSPT857APAI datasheet(6/12 Pages) IDT

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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDTCSPT857/A

2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

TIMING REQUIREMENTS

Symbol

Parameter

Min.

Max.

Unit

fCLK

OperatingClockFrequency(1,2)

200

MHz

ApplicationClockFrequency(1,3)

200

MHz

tDC

Input Clock Duty Cycle

StabilizationTime(4)



100

µs

NOTES:

1. The PLL will track a spread spectrum clock input.

2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.

3. Application clock frequency is the range over which timing specifications apply.

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.

SWITCHINGCHARACTERISTICS

CSPT857

CSPT857A

Symbol

Description

Test Conditions

Min. Typ.(1) Max.

Min. Typ.(1)

Max.

Unit

tPLH(1)

LOW to HIGH Level Propagation Delay Time

Test mode, CLK to any output

4.5

tPHL(1)

HIGH to LOW Level Propagation Delay Time

Test mode, CLK to any output

4.5

tJIT(PER)

Jitter(period),seefigure6

66MHz

– 90

100/ 133/ 167/ 200 MHz

– 75

tJIT(CC)

Jitter(cycle-to-cycle),seefigure3

66MHz

–180

180

–180

180

100/ 133/ 167/ 200 MHz

– 75

tJIT(HPER)

Half-PeriodJitter,seefigure7

66MHz

–160

160

–160

160

100/ 133/ 167/ 200 MHz

–100

100

–100

100

tSLR(O)

OutputClockSlewRate(Single-Ended)

100/ 133/ 167/ 200 MHz (20% to 80%)

V/ns

tSLR(I)

Input Clock Slew Rate

V/ns

t(∅)

StaticPhaseOffset,seefigure4(2,3)

66/ 100/ 133/ 167/ 200 MHz

–100

100

– 50

tSK(O)

Output Skew, see figure 5

tR,tF

Output Rise and Fall Times (20% to 80%)

Load: 120

Ω / 14pF

650

900

650

900

VOX(5)

OutputDifferentialVoltage

Differentialoutputsareterminated

VDDQ/2

VDDQ/2 VDDQ/2

VDDQ/2

with 120

Ω

– 0.2

+ 0.2 –0.15

+ 0.15

The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:

SSC

ModulationFrequency



KHz

SSC

ClockInputFrequencyDeviation



-0.5



-0.5

f3dB

PLLLoopBandwidth





MHz

NOTES:

1. Refers to transition of non-inverting output.

2. Static phase offset does not include jitter.

3. t(

φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.

4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.

5. VOX is specified at the SDRAM clock input or test load.

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