CDC305

OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995

4

POST OFFICE BOX 655303

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

fmax‡

80

MHz

tPLH

CLK

QQ

RL = 500 Ω

CL =50 pF

2

6

9

ns

tPHL

CLK

Q, Q

RL = 500 Ω,

CL = 50 pF

2

6

9

ns

tPLH

PRE or CLR

QQ

RL = 500 Ω

CL =50 pF

3

7

12

ns

tPHL

PRE or CLR

Q, Q

RL = 500 Ω,

CL = 50 pF

3

7

12

ns

Q

R

500

Ω

C

10F t30F

1

tsk(o)

CLK

Q

RL = 500 Ω,

See Figure 2

CL = 10 pF to 30 pF,

1

ns

()

Q1– Q8

See Figure 2

1.5

t k( )

CLK

Q1, Q8

RL = 500 Ω

CL =10 pFto30 pF

1.5

ns

tsk(p)

CLK

Q2 – Q7

RL = 500 Ω,

CL = 10 pF to 30 pF

2

ns

tr

4.5

ns

tf

3.5

ns

† All typical values are at VCC = 5 V, TA = 25°C.

‡ fmax minimum values are at CL = 0 to 30 pF.

PARAMETER MEASUREMENT INFORMATION

CLK

Q

3.5 V

VOL

0.3 V

1.3 V

tsu

From Output

Under Test

LOAD CIRCUIT

Test Point

CLR

or

PRE

1.3 V

1.3 V

1.3 V

VOH

CL

(see Note A)

tPLH

tPHL

RL

tw

1.3 V

3.5 V

0.3 V

NOTES: A. CL includes probe and jig capacitance.

B. Input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms