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STM32WB55CC bảng dữ liệu(PDF) 125 Page - STMicroelectronics

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STM32WB55CC bảng dữ liệu(HTML) 125 Page - STMicroelectronics

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DS11929 Rev 3
125/165
STM32WB55xx
Electrical characteristics
152
Figure 23. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 71: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
Table 71. NRST pin characteristics(1)
1.
Guaranteed by design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input
low level voltage
-
-
-
0.3 x VDD
V
VIH(NRST)
NRST input
high level voltage
-
0.7 x VDD
--
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
--
200
-
mV
RPU
Weak pull-up
equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order)
.
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST input
filtered pulse
--
-
70
ns
VNF(NRST)
NRST input
not filtered pulse
1.71 V ≤ VDD ≤ 3.6 V
350
-
-



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