COPCH982C datasheet(14/31 Pages) NSC

14 / 31 page

Functional Description (Continued)

DETECTION OF ILLEGAL CONDITIONS

The device contains a hardware mechanism that allows it to

detect illegal conditions which may occur from coding errors,

noise and “brown out” voltage drop situations. Specifically it

detects cases of executing out of undefined ROM area and

unbalanced stack situations.

Reading an undefined ROM location returns 00 (hexadeci-

mal) as its contents. The opcode for a software interrupt is

also “00”. Thus a program accessing undefined ROM will

cause a software interrupt.

Reading an undefined RAM location returns an FF (hexa-

decimal). The subroutine stack grows down for each subrou-

tine call. By initializing the stack pointer to the top of RAM,

the first unbalanced return instruction will cause the stack

pointer to address undefined RAM. As a result the program

will attempt to execute from FFFF (hexadecimal), which is an

undefined ROM location and will trigger a software interrupt.

MICROWIRE/PLUS

MICROWIRE/PLUS is a serial synchronous bidirectional

communications interface. The MICROWIRE/PLUS capabil-

ity enables the device to interface with any of National

Semiconductor’s MICROWIRE peripherals (i.e. A/D convert-

ers, display drivers, EEPROMS, etc.) and with other micro-

controllers which support the MICROWIRE/PLUS interface.

It consists of an 8-bit serial shift register (SIO) with serial

data input (SI), serial data output (SO) and serial shift clock

(SK).

Figure 7 shows the block diagram of the MICROWIRE/

PLUS interface.

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS

interface with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS interface with an external shift clock is called the Slave

mode of operation.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. The SK

clock rate is selected by the two bits, SL0 and SL1, in the

CNTRL register.

Table 3 details the different clock rates that

may be selected.

TABLE 3.

SL1

SL0

SK Cycle Time

where,

C is the instruction cycle clock.

MICROWIRE/PLUS OPERATION

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS arrangement to start shifting the data. It

gets reset when eight data bits have been shifted. The user

may reset the BUSY bit by software to allow less than 8 bits

to shift. The devoce may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave.

Figure 8 shows how

two COP880C microcontrollers and several peripherals may

be interconnected using the MICROWIRE/PLUS arrange-

ment.

Master MICROWIRE/PLUS Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally. The MICROWIRE/

PLUS Master always initiates all data exchanges. (See

Fig-

ure 8). The MSEL bit in the CNTRL register must be set to

enable the SO and SK functions onto the G Port. The SO

and SK pins must also be selected as outputs by setting

appropriate bits in the Port G configuration register.

Table 4

summarizes the bit settings required for Master mode of

operation.

SLAVE MICROWIRE/PLUS OPERATION

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by appropriately

setting up the Port G configuration register.

Table 4 summa-

rizes the settings required to enter the Slave mode of opera-

tion.

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated. (See

Figure 8.)

DS010802-8

FIGURE 6. Interrupt Block Diagram

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