ADPA7002CHIP datasheet(15/23 Pages) AD

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Data Sheet

ADPA7002CHIP

Rev. 0 | Page 15 of 23

THEORY OF OPERATION

The architecture of the ADPA7002CHIP, a medium power

amplifier, is shown in Figure 52. The ADPA7002CHIP uses a

cascaded, three-stage amplifier operating in quadrature

between two 90° hybrids.

The input signal is evenly divided into two. Each input signal is

amplified through three independent gain stages and the amplified

signals are combined at the output. This balanced amplifier

approach creates an amplifier with a combined gain of 15 dB

and a PSAT value of 30 dBm.

A portion of the RF output signal is directionally coupled to a

diode to detect the RF output power (see Figure 52). When the

diode is dc biased, the diode rectifies the RF power and makes

the RF power available for measurement as a dc voltage at the

VDET pin. Temperature compensation is accomplished by

referencing a symmetrical diode circuit that is not coupled to

the RF output, which contains a dc voltage output, at the VREF

pin as shown in Figure 56. The difference of VREF − VDET

provides a temperature compensated signal that is proportional

to the RF output.

The 90° hybrids ensure that the input and output return losses

are >12 dB. See the application circuits in Figure 53 and

Figure 54 for further details on biasing the various blocks.

To obtain optimal performance from the ADPA7002CHIP and

avoid damaging the device, follow the recommended biasing

sequences described in the Biasing Procedures section.

Figure 52. Fundamental Cell Schematic

RFIN

RFOUT

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