AD9175 datasheet(17/150 Pages) AD

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Data Sheet

AD9175

Rev. A | Page 17 of 150

Pin No.

Mnemonic

Description

Sync Output

D12

SYNCOUT0+

Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or

CMOS selectable.

D11

SYNCOUT0−

Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or

CMOS selectable.

SYNCOUT1+

Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or

CMOS selectable.

SYNCOUT1−

Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or

CMOS selectable.

Serial Port Interface

SDO

Serial Port Data Output (CMOS Levels with Respect to DVDD1.8).

SDIO

Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8).

SCLK

Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8).

Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8).

RESET

Reset, Active Low (CMOS Levels with Respect to DVDD1.8).

Interrupt Request

IRQ0

Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels

with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this

pin from floating when inactive.

IRQ1

Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels

with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this

pin from floating when inactive.

CMOS Input/Outputs

TXEN0

Transmit Enable for DAC0. The CMOS levels are determined with respect to

DVDD1.8.

TXEN1

Transmit Enable for DAC1. The CMOS levels are determined with respect to

DVDD1.8.

DAC Analog Outputs

DAC0+

DAC0 Positive Current Output.

DAC0−

DAC0 Negative Current Output.

DAC1+

DAC1 Positive Current Output.

DAC1−

DAC1 Negative Current Output.

Reference

L12

ISET

Device Bias Current Setting Pin. Connect a 5 kΩ resistor from this pin to GND,

preferably with <0.1% tolerance and <±25 ppm/°C temperature coefficient.

Do Not Connect

E1, E2, E11, E12, J2, K4

DNC

Do Not Connect. Do not connect to these pins.

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