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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AD9174 bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD9174 bảng dữ liệu(HTML) 10 Page - Analog Devices |
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10 / 164 page  AD9174 Data Sheet Rev. A | Page 10 of 164 DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LATENCY1 Channel Interpolation Factor, Main Datapath Interpolation Factor LMFC_VAR_x = 12, LMFC_DELAY_x = 12, unless otherwise noted 1×, 1×2 JESD204B Mode 10,3 Mode 183 420 DAC clock cycles JESD204B Mode 11, Mode 19 440 DAC clock cycles JESD204B Mode 12, Mode 19 590 DAC clock cycles JESD204B Mode 203 700 DAC clock cycles JESD204B Mode 21 750 DAC clock cycles 1×, 2×2 JESD204B Mode 83 670 DAC clock cycles JESD204B Mode 9 700 DAC clock cycles 1×, 4×2 JESD204B Mode 83 1090 DAC clock cycles JESD204B Mode 9 1140 DAC clock cycles 1×, 6×2 JESD204B Mode 83 1460 DAC clock cycles JESD204B Mode 9 1530 DAC clock cycles 1×, 8×2 JESD204B Mode 3 1390 DAC clock cycles JESD204B Mode 83 1820 DAC clock cycles JESD204B Mode 9 1920 DAC clock cycles 1×, 12×2 JESD204B Mode 83 2700 DAC clock cycles JESD204B Mode 9 2840 DAC clock cycles 2×, 6×2 JESD204B Mode 3, Mode 4 1970 DAC clock cycles JESD204B Mode 5 1770 DAC clock cycles 2×, 8×2 JESD204B Mode 0 2020 DAC clock cycles JESD204B Mode 3, Mode 4 2500 DAC clock cycles 3×, 6×2 JESD204B Mode 3, Mode 4 2880 DAC clock cycles JESD204B Mode 5, Mode 6 2630 DAC clock cycles 3×, 8×2 JESD204B Mode 3, Mode 4 3310 DAC clock cycles JESD204B Mode 5, Mode 6 2980 DAC clock cycles 4×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 2410 DAC clock cycles 4×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 3090 DAC clock cycles 6×, 6×2 JESD204B Mode 0, Mode 1, Mode 2 3190 DAC clock cycles 6×, 8×2 JESD204B Mode 0, Mode 1, Mode 2 4130 DAC clock cycles 8×, 6×2 JESD204B Mode 7 3300 DAC clock cycles 8×, 8×2 JESD204B Mode 7 4270 DAC clock cycles DETERMINISTIC LATENCY Fixed 13 PCLK4 Variable 2 PCLK cycles SYSREF± TO LMFC DELAY 0 DAC clock cycles 1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay. 2 The first value listed in this specification is the channel interpolation factor, and the second value is the main datapath interpolation factor. 3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4 4 PCLK is the internal processing clock for the AD9174 and equals the lane rate ÷ 40. |
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