EVAL-AD4111SDZ datasheet(49/59 Pages) AD

49 / 59 page

Data Sheet

AD4111

Rev. A | Page 49 of 59

Bits

Bit Name

Settings

Description

Reset

Access

[3:0]

Channel

These bits indicate which channel was active for the ADC conversion

whose result is currently in the data register. This may be different from

the channel currently being converted. The mapping is a direct map from

the channel register. Therefore, Channel 0 results in 0x0 and Channel 15

results in 0xF.

0x0

0000

Channel 0.

0001

Channel 1.

0010

Channel 2.

0011

Channel 3.

0100

Channel 4.

0101

Channel 5.

0110

Channel 6.

0111

Channel 7.

1000

Channel 8.

1001

Channel 9.

1010

Channel 10.

1011

Channel 11.

1100

Channel 12.

1101

Channel 13.

1110

Channel 14.

1111

Channel 15.

ADC MODE REGISTER

Address: 0x01, Reset: 0x2000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets

the filter and the RDY bits and starts a new conversion or calibration.

Table 26. Bit Descriptions for ADCMODE

Bits

Bit Name

Settings

Description

Reset

Access

REF_EN

Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin.

0x0

Disabled.

Enabled.

Reserved

This bit is reserved. Set this bit to 0.

0x0

SING_CYC

This bit can be used when only a single channel is active to set the ADC to

only output at the settled filter data rate.

0x1

Disabled.

Enabled.

[12:11]

Reserved

These bits are reserved. Set these bits to 0.

0x0

[10:8]

Delay

These bits allow a programmable delay to be added after a channel switch

to allow the settling of external circuitry before the ADC starts processing

its input.

0x0

000

0 µs.

001

32 µs.

010

128 µs.

011

320 µs.

100

800 µs.

101

1.6 ms.

110

4 ms.

111

8 ms.

Reserved

This bit is reserved. Set this bit to 0.

0x0

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