AD5753 datasheet(16/72 Pages) AD

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AD5753

Data Sheet

Rev. 0 | Page 16 of 72

Pin No.

Mnemonic

Description

CLKOUT

Optional Clock Output Signal (Disabled by Default). This pin is a divided down version of the internal 10 MHz

internal oscillator, which generates the master clock (MCLK), and is configured in the GP_CONFIG1 register.

SCLK

Serial Clock Input. Data is clocked to the input shift register on the falling edge of the SCLK. In write mode, this pin

operates at clock speeds of up to 50 MHz and this speed is dependent on the VLOGIC voltage. In read mode, the maximum

SCLK speed is 15 MHz and this speed is dependent on the VLOGIC voltage. See Table 3 for the timing specifications.

SDI

Serial Data Input. Data must be valid on the falling edge of SCLK.

SYNC

Frame Synchronization Signal for the Serial Interface. Active low input. While SYNC is low, data is transferred in on

the falling edge of SCLK.

AD1

Address Decode 1 for the AD5753 Device.

AD0

Address Decode 0 for the AD5753 Device.

FAULT

Fault Pin. Active low, open-drain output. This pin is high impedance when no faults are detected and is asserted

low when certain faults are detected. Some of these faults include an open circuit in current mode, a short circuit

in voltage mode, a CRC error, or an overtemperature error (see the Output Fault section). This pin must be connected to

VLOGIC with a 10 kΩ pull-up resistor.

NIC

Not Internally Connected.

AVSS

Negative Analog Supply. The voltage range on this pin is 0 V to −33 V. If using the device solely for unipolar current

output purposes, the AVSS can be set to 0 V. For a unipolar voltage output, AVSS (maximum) is −2 V. When using

bipolar output ranges, the VOUT or IOUT headroom must be obeyed when calculating the AVSS maximum. For

example, for a ±10 V output, the AVSS maximum is −12.5 V. See the AVSS Considerations section for an important

note on power supply sequencing.

SW−

Switching Output for the Negative DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect the pin

and external inductor as shown in Figure 78.

PGND2

Power to Ground.

VDPC−

Negative Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect the

external capacitor as shown in Figure 78.

NIC

Not Internally Connected.

−VSENSE

Sense Connection for Negative Voltage Output Load Connection for VOUT Mode. This pin must stay within ±10 V of

AGND for specified operation. For specified operation, VDPC− tracks −VSENSE with respect to AGND. It is

recommended to connect a series 1 kΩ resistor to this pin.

CCOMP

Optional Compensation Capacitor Connection for the Voltage Output Buffer. Connecting a 220 pF capacitor

between this pin and the VIOUT pin allows the voltage output to drive up to 2 µF. The addition of this capacitor

reduces the bandwidth of the output amplifier, increasing the settling time.

+VSENSE

Sense Connection for Positive Voltage Output Load Connection for Voltage Output Mode. It is recommended to

connect a series 1 kΩ resistor to this pin.

VIOUT

Voltage or Current Output Pin. VIOUT is a shared pin that provides either a buffered output voltage or current.

ADC2

Multiplexed ADC External Input 2.

VDPC+

Positive Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect the

external capacitor as shown in Figure 77.

PGND1

Power to Ground.

EPAD

Exposed Pad. Connect the exposed pad to the potential of the VDPC− pin, or, alternatively, the exposed pad can be left

electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced

thermal performance.

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