AD4112BCPZ datasheet(49/58 Pages) AD

49 / 58 page

Data Sheet

AD4112

Rev. A | Page 49 of 58

Bits

Bit Name

Settings

Description

Reset

Access

[6:4]

Mode

These bits control the operating mode of the ADC. See the Operating

Modes section for more information.

0x0

000

Continuous conversion mode.

001

Single conversion mode.

010

Standby mode.

011

Power-down mode.

100

Internal offset calibration.

101

Internal gain calibration

110

System offset calibration.

111

System gain calibration.

[3:2]

CLOCKSEL

These bits select the ADC clock source. Selecting the internal oscillator

also enables the internal oscillator.

0x0

Internal oscillator.

Internal oscillator output on the XTAL2/CLKIO pin.

External clock input on the XTAL2/CLKIO pin.

External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.

[1:0]

Reserved

These bits are reserved; set these bits to 0.

0x0

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The interface mode register configures various serial interface options.

Table 27. Bit Descriptions for IFMODE

Bits

Bit Name

Settings

Description

Reset

Access

[15:13]

Reserved

These bits are reserved; set these bits to 0.

0x0

ALT_SYNC

This bit enables a different behavior of the SYNC pin to allow the use of

SYNC as a control for conversions when cycling channels

0x0

Disabled.

Enabled.

IOSTRENGTH

This bit controls the drive strength of the DOUT/RDY pin. Set this bit when

reading from the serial interface at high speed with a low IOVDD supply

and moderate capacitance.

0x0

Disabled (default).

Enabled.

[10:9]

Reserved

These bits are reserved; set these bits to 0.

0x0

DOUT_RESET

See the DOUT_RESET section

0x0

Disabled.

Enabled.

CONTREAD

This bit enables the continuous read mode of the ADC data register. The ADC

must be configured in continuous conversion mode to use continuous

read mode. For more details, see the Operating Modes section.

0x0

Disabled.

Enabled.

DATA_STAT

This bit enables the status register to be appended to the data register

when read so that channel and status information are transmitted with

the data. This is the only way to be sure that the channel bits read from

the status register correspond to the data in the data register.

0x0

Disabled.

Enabled.

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