10 / 25 page
C9827H
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 10 of 25
Approved Product
Maximum Lumped Capacitive Output
Loads
Clock
Max Load
Units
PCI Clocks
30
pF
3V66 (0,1)
30
pF
66B(0:2)
30
pF
48MUSB Clock
20
pF
48MDOT
10
pF
REF Clock
30
pF
Table 5
Maximum Ratings¹
Input Voltage Relative to VSS:
VSS-0.3V
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
Storage Temperature:
-65
°C to + 150°C
Operating Temperature:
0
°C to +85°C
Maximum Power Supply:
3.5V
Note 1: The voltage on any input or I/o pin cannot exceed the
power pin during power-up. Power supply sequencing is NOT
required.
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK Measurement Point
R
ref
R
tA1
CLK
CLK#
Mult0
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
Lumped Test Load Configuration
Component
0.7 Volt Amplitude Value
1.0 Volt Amplitude Value
RtA1, RtA2
33
Ω
0
Ω
RLA1, RLA2
49.9
Ω∞
TPCB
3” 50
ΩZ
3” 50
ΩZ
RLB1, RLB2
∞
63
Ω
RD
∞
470
Ω
RtB1, RtB2
0
Ω
33
Ω
CLA, CLB
2pF
2 pF
Rref
475
Ω w/mult0=1
221
Ω w/mult0=0
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
