T25D40AFIPR datasheet(33/74 Pages) HMSEMI

33 / 74 page

7. INSTRUCTIONS

The instruction set of the

HM25Q128A consists of forty basic instructions that are fully controlled through

the SPI bus. Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked

into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with

most significant bit (MSB) first.

The QPI instruction set of the

HM25Q128A consists of 32 basic instructions that are fully controlled

through the SPI bus (see Instruction Set Table 7.5). Instructions are initiated with the falling edge of Chip

Select (CS#). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four

IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions,

addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial

clocks (CLK).

Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data

bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising

edge of edge CS#. Clock relative timing diagrams for each instruction are included in figures 7.1 through 7.47

All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or

Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the

instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while

the memory is being programmed or erased, or when the Status Register is being written, all instructions

except for Read Status Register and Erase/Program Suspend will be ignored until the program or erase cycle

completes.

HM25Q128A

T25D40AFIPR bảng dữ liệu(PDF) 33 Page - Shenzhen Huazhimei Semiconductor Co., Ltd