GD25WD80CPIG datasheet(13/47 Pages) GIGADEVICE

tên linh kiện	GD25WD80CPIG

Giải thích chi tiết về linh kiện	Uniform Sector Standard and Dual Serial Flash

PDF	47 Pages

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13 / 47 page

Uniform Sector

Standard and Dual Serial Flash

GD25WD80C

7.1. Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable Latch

(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write

Status Register (WRSR) command.

The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enable command  CS# goes

high.

Figure1. Write Enable Sequence Diagram

7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by following

condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip

Erase commands.

The Write Disable command sequence: CS# goes lowSending the Write Disable command CS# goes high.

Figure2. Write Disable Sequence Diagram

Command

06H

CS#

SCLK

High-Z

Command

04H

CS#

SCLK

High-Z

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