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GD25VQ40CSIG bảng dữ liệu(PDF) 35 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25VQ40CSIG bảng dữ liệu(HTML) 35 Page - GigaDevice Semiconductor (Beijing) Inc. |
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35 / 56 page ![]() Uniform Sector Dual and Quad Serial Flash GD25VQ40C 35 initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security Registers command will be ignored. Address A23-A16 A15-A8 A7-A0 Security Registers 0 00H 00H Byte Address Security Registers 1 00H 01H Byte Address Security Registers 2 00H 02H Byte Address Security Registers 3 00H 03H Byte Address Figure33. Program Security Registers command Sequence Diagram 7.29. Read Security Registers (48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A7-A0 address reaches the last byte of the register (Byte FFH), it will reset to 000H, the command is completed by driving CS# high. Address A23-A16 A15-A8 A7-A0 Security Registers 0 00H 00H Byte Address Security Registers 1 00H 01H Byte Address Security Registers 2 00H 02H Byte Address Security Registers 3 00H 03H Byte Address Command 0 1 2 3 4 5 6 7 42H CS# SCLK SI 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 32 33 34 35 7 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 36 37 38 39 |
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