GD25S513MDBFG datasheet(19/94 Pages) GIGADEVICE

tên linh kiện	GD25S513MDBFG

Giải thích chi tiết về linh kiện	3.3V Uniform Sector Dual and Quad Serial Flash

PDF	94 Pages

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19 / 94 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25S513MD

output timing on 4 I/O pins. When DLP=1, during the last 4 dummy clocks just prior to the data output, the flash will output

“00110100” Data Learning Pattern sequence on each of the 4 I/O pins. During this period, controller can fine tune the data

latching timing for each I/O pins to achieve optimum system performance. Setting DLP=0 will disable the Data Learning

Pattern output. The Data Learning Pattern can also be defined by a “Write Data Learning Pattern (4AH)” command followed

by 8-bit user-defined pattern. The user defined pattern is volatile. After the device power-up cycle, the Data Learning Pattern

will return to its “00110100” default value.

ECS bit

The ECS bit is ECC Correction Signal bit, which is volatile writable by 56H command. The hardware ECS# Pin is used

by the system to detect ECC events during Read operations when ECC is enabled (ECC=1). When ECS=0, the ECS# Pin

will be pulled low during the aligned 8-Byte data output period if there is a SEC (Single Error Correction) event within the 8-

Byte ECC granularity. When ECS=1, the ECS# Pin will be pulled low for DED (Double Error Detection) events. When ECC

is disabled (ECC=0), the ECS bit value is ignored and ESC# Pin is disabled.

GD25S513MDBFG bảng dữ liệu(PDF) 19 Page - GigaDevice Semiconductor (Beijing) Inc.