GD25Q40CSFG datasheet(23/64 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q40C

7.12.

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address

bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15. The first byte

addressed can be at any location. The address is automatically incremented to the next higher address after each byte of

data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read

command.

Quad I/O Word Fast Read with “Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous

Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the

next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code.

The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than

AXH, the next command require

s the first E7H command code, thus returning to normal operation. A “Continuous Read

Mode” Reset command can be used to reset (M7-0) before issuing normal command.

Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

Figure 16. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)

Command

E7H

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

WP#(IO2)

HOLD#(IO3)

Dummy

Byte1 Byte2

Byte3

CS#

SCLK

9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

A23-16 A15-8 A7-0

M7-0 Dummy Byte1 Byte2

Byte3

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