GD25Q127CSJS datasheet(25/79 Pages) GIGADEVICE

25 / 79 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q127C

afterwards within a fixed length (8/16/32/64-

byte) of data without issuing multiple read commands. The “Set Burst with Wrap”

command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation

while W6-W5 is used to specify the length of the wrap around section within a page.

7.12.

Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first

byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte

of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast

read command.

Quad I/O Word Fast Read with

“Continuous Read Mode”

The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous

Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then

the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command

code. The command sequence is shown in followed Figure14a

.If the “Continuous Read Mode” bits (M5-4) do not equal to

(1, 0), the next command requires the fir

st E7H command code, thus returning to normal operation. A “Continuous Read

Mode” Reset command can be used to reset (M5-4) before issuing normal command.

Figure14. Quad I/O Word Fast Read Sequence Diagram (M5-

4≠ (1, 0))

Figure14a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))

Command

E7H

CS#

SCLK

SI(IO0)

SO(IO1)

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23

A23-16 A15-8 A7-0

M7-0

WP#(IO2)

HOLD#(IO3)

Dummy

Byte1 Byte2

Byte3

CS#

SCLK

9 10 11 12 13 14 15

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

A23-16 A15-8 A7-0

M7-0 Dummy Byte1 Byte2

Byte3

GD25Q127CSJS bảng dữ liệu(PDF) 25 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25Q127CSJS bảng dữ liệu(HTML) 25 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

bảng dữ liệu tải về

Link URL