GD25R256D datasheet(16/82 Pages) GIGADEVICE

16 / 82 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25R256D

7. COMMANDS DESCRIPTION

All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the

first rising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with

most significant bit first on SI, and each bit being latched on the rising edges of SCLK.

Every command sequence starts with a one-Byte command code. Depending on the command, this might be followed

by address Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command sequence

has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down,

and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be

completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to

deselected status.

For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,

Write Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command

is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven

low is an exact multiple of eight. For Page Program, if at any time the input Byte is not a full Byte, nothing will happen and

WEL will not be reset.

When the device is in 3-Byte address mode (ADS=0), please refer to command set in table13 & table14. When the

device is in 4-Byte address mode (ADS=1), please refer to command set in table13 & table15.

Extended Address Register setting is effective to achieve A31-A24, accompanying A23-A0 within the instruction, when

commands listed in table14 are executed.

Extended Address Register setting is ignored when A31-A24 are given in the instruction listed in table 15 and some

specific instruction from table13 (13H, 0CH, 3CH, 6CH, BCH, ECH).

Table 13. Commands (Standard/Dual/Quad SPI, 3-Byte & 4-Byte address mode)

Command

Name

Add

Mode

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

n-Bytes

Write Enable

3 & 4

06H

Write Disable

3 & 4

04H

Volatile SR

Write Enable

3 & 4

50H

Read Status

3 & 4

05H

(S7-S0)

(cont.)

Read Status

3 & 4

35H

(S15-S8)

(cont.)

Read Status

3 & 4

15H

(S23-S16)

Write Status

3 & 4

01H

S7-S0

Write Status

3 & 4

01H

S7-S0

S15-S8

Write Status

3 & 4

31H

S15-S8

Write Status

3 & 4

11H

S23-S16

Read

Extended

Addr. Register

3 & 4

C8H

(EA7-EA0)

Write

Extended

Addr. Register

3 & 4

C5H

EA7-EA0

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