GD25LE256DFES datasheet(28/83 Pages) GIGADEVICE

tên linh kiện	GD25LE256DFES

Giải thích chi tiết về linh kiện	1.8V Uniform Sector Dual and Quad Serial Flash

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE256D

7.10. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) or a 4-byte address (A31-A0) and a

dummy byte, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock

cycle from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any

location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The

default read mode is 3-byte address mode, and the lower 128Mbit can be read with a single Dual Output Fast Read (3BH)

command. By entering 4-byte address mode, or to set EN4B (S11) bit to 1, the higher 128Mbit can be read with a single

Dual Output Fast Read (3BH) command.

Figure11. Dual Output Fast Read Sequence Diagram

Command

3BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Clocks

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

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