GD25LB256D datasheet(42/79 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LB256D

7.20. 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is

entered by driving CS# low, followed by the command code, and 3-byte address or 4-byte address on SI. Any address

inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration

of the sequence.

The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte address

or 4-byte address on SI  CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after

the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed.

As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase

cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in

Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a

block which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.

Figure20. 64KB Block Erase Sequence Diagram

Command

D8H

CS#

SCLK

29 30 31

MSB

24 Bits Address

23 22

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

Figure20a. 64KB Block Erase Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

D8H

A23-16 A15-8

A7-0

22 18

21 17

Note: The device default is in 24-bit address mode. For 4-byte mode, the address length becomes 32-bit.

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